Conventional phase locked loop (PLL) circuits fall generally into two categories: analog and digital. Both PLL categories suffer from drawbacks.
Fully analog PLLs typically include a phase frequency detector (PFD), a charge pump (CP), a divider, and an analog loop filter for settling a control voltage that is supplied to, and controls, a voltage controlled oscillator (VCO). When used for frequency synthesis, analog techniques suffer from the following drawbacks: large area of the passive components of the loop filter, and conflict between noise performance (requiring narrow band circuits) and settling time (requiring wide band circuits). When used for phase or frequency modulation, analog techniques also have shortcomings. As one example, analog techniques do not allow direct modulation of the VCO because of the large variations of the VCO gain over process, temperature and frequency.
In an effort to overcome the drawbacks of the fully analog PLLs, fully digital PLLs have been proposed. Typically, digital PLLs include digital filters, time to digital converters (TDC), and high order rate sigma/delta (SD) converters. In addition to relatively high cost, fully digital PLLs suffer from slow acquisition and settling time, higher noise levels, limited frequency resolution, and high complexity.